UNIT IV: Memory and I/O Interfacing Questions and Notes

UNIT IV: 

Memory and I/O Interfacing: Minimum and Maximum mode configuration of 8086, Memory Interface with 8086 microprocessor, Address Decoding. Basic I/O Interface: Introduction to I/O Interface, I/O Port Address Decoding. I/O Interface using peripheral devices: The Programmable Peripheral Interface 8255, Programmable Interval Timer 8254. Direct Memory Access: Basic DMA Operation and Definition.

Syllabus Source: 

https://csvtu.ac.in/ew/download/b-tech-5th-semester-5/?wpdmdl=14364&refresh=63bfa9631ce311673505123

👉Prerequisite:

We have to Learn to do following with 8086.

1. Memory Interfacing 

2. I/O Interfacing

😃Study Block Diagram of the Following (SEE CLASS NOTES TO UNDERSTAND  TOPICs) 

i. Minimum and Maximum mode configuration of 8086.

ii. Memory Interface (RAM and EPROM) with 8086.

iii. Programmable Peripheral Interface 8255.

iv. Programmable Interval Timer 8254.

v. Direct Memory Access .

Questions : Compiled from Previous CSVTU Question papers

Topic: Memory Interface (RAM and EPROM) with 8086: 

Needed: Address Mapping and Decoding Circuit

👱see class notes

Q. Design an interface between 8086 and two chips of 16K x 8 EPROM (=16KB) and two chips of 32K × 8 RAM (=32KB). Select the starting location of the EPROM suitably. RAM location must start from 00000H. 

Q. Give 8086 Memory Interfacing diagram for 32KB RAM using 16KB RAM and 16KB EPROM using 8KB EPROM, use partial Decoding. 

Q. Interface two 4K X 8 EPROMs and two 4K X 8 RAM chips with 8086 microprocessor. Select Suitable Maps. 

Q. Interface two 8K X 8 EPROMs and four 16K X 8 RAM chips with 8086 microprocessor. The address range is as follows: EPROM 1 & 2: END address is FFFFFH; RAM 1 & 2: Start Address is 10000H; RAM 3 & 4: END address is 1FFFFH. 

Q. Connect a 32kB RAM with the microprocessor 8086 using an absolute decoding with suitable address.

Example problems on memory interfacing with 8086 

(Ref: Advanced Microprocessors and Peripherals by A.K. Ray & K.M. Bhurchandi, 

McGraw-Hill, 2nd Edition.P.158- 164)

😄Beyond Syllabus:

if you want to Know how a DYNAMIC RAM  D-RAM 1-T (One Transistor ) based works , see my video:

Topic: I/O Interface with 8086: 

Needed: Block Diagrams 

Q. Explain 8254 functional Block Diagram.

Ans: 

PROGRAMMABLE INTERVAL TIMER 8254

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. 

8254 is the high speed version of the 8253. 

Application Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are: 

 Real time clock 

 Event-counter 

 Digital one-shot 

 Programmable rate generator 

 Square wave generator 

 Binary rate multiplier 

 Complex waveform generator 

 Complex motor controller

 8254 PROGRAMMABLE INTERVAL TIMER functional Block Diagram: 

It includes Three 16-bit counters COUNTER 0, COUNTER 1, COUNTER3  that can work independently in 6 different modes. 

Modes of Operation 

Mode 0: Interrupt on terminal count. 

Mode 1: Hardware Re triggerable One-Shot. 

Mode 2: Rate Generator. 

Mode 3: Square Wave Mode. 

Mode 4: Software Triggered Mode. 

Mode 5: Hardware Triggered Mode

 It is packaged in a 24-pin DIP(Dual in-line package) and requires +5V power supply. 

 It can count either in binary or BCD. 

 It’s counters can operate at a maximum frequency of 10 MHz's.

Pin functions: 

               A0, A1: The address inputs select one of the four internal registers within the 8254. 

 𝐂𝐒: Chip select enables the 8254 for programming and for reading or writing a counter. 

              Vcc: Power connects to the +5V power supply. 

              GND: Ground connects to the system ground bus. 

              GATE : The gate input controls the operation of the counter in some modes of operation. 

               D0-D7: Bidirectional three state data bus lines connected to system data bus. 

 

               CLK : The clock input is the timing source for each of the internal counters. This input is often  connected to the PCLK signal from the microprocessor system bus controller. 

               OUT: A counter output is where the waveform generated by the counter is available. 

 

 

            𝐑𝐃: Read causes data to be read from the 8254 and often connected to the 𝐼𝑂𝑅𝐶 signal. 

            𝐖𝐑: Write causes data to be written to the 8254 and often connects to the write strobe (𝐼𝑂𝑊𝐶) 

Pin.

Programming the 8254 (Control Word Format)

8254 Write operation :

The programming procedure for the 8254 is very flexible. 

Only two conversion need to be remember. 

1) For each Counter, the Control Word must be written before the initial count is written. 

2) The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). 

With a clock and an appropriate gate signal to one of the counters, the above steps should start the counter and provide appropriate output according to the control word.

Q. Explain the functional block diagram of 8255 PPI.

Ans:

8255 PPI

8255 PPI (Programmable Peripheral Interface)

It is a programmable peripheral interface, which means it is a programmable device used to interface I/O devices with the processor.

8255 is a programmable I/O device that acts as interface between peripheral devices and the microprocessor for parallel data transfer. 

8255 PPI (programmable peripheral interface) is programmed in a way so as to have transfer of data in different conditions according to the need of the system.

The common applications of 8255 are: 
 

• Traffic light control
• Generating square wave
• Interfacing with DC motors and stepper motors

Architecture of 8255: 

In 8255, 

The three ports are Port A, Port B and Port C and as each port has 8 lines, but the 8 bits of port C is divided into 2 groups of 4-bit each. These are given as port C lower i.e., PC3 – PC0 and port C upper i.e., PC7 – PC4. 

And are arranged in group of 12 pins each thus designated as Group A and Group B.

  

Modes of 8255 – It works in two modes: 
 

1. Bit set reset (BSR) mode.
2. Input/output (I/O) mode.

I/O mode is further classified into:

Mode 0: Simple input/output
Mode 1: Input output with handshaking

Mode 2: Bidirectional I/O hand shaking

To know in which mode the interface is working we need to know the value of Control word. Control word is a part of control register in 8255 which specify an I/O function for each port. This is format of control word 8255.

Example: 

Q. Explain the Basic DMA operation.

Ans: 

Microprocessor - 8257 DMA Controller

Definition: DMA or Direct Memory Access Controller is an external device that controls the transfer of data between I/O device and memory without the involvement of the processor. It holds the ability to directly access the main memory for read or write operation.

DMA controller was designed by Intel, to have the fastest data transfer rate with less processor utilization.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

• 1. Initially, when any device has to send data between the device and the memory, the device has to send DMA request (DRQ) to DMA controller.

• 2. The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.

• 3. Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control over bus and acknowledges the HOLD request through HLDA signal.

• 4.Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses between the CPU, memory, and I/O devices.

  

• 8257:
• DRQo- DRQ3: These are the four individual channel DMA request inputs, used by the peripheral devices for requesting the DMA services. The DRQo has the highest priority while DRQ3 has the lowest one, if the fixed priority mode is selected. 
• DACKo- DACK3: These are the active- low DMA acknowledge output lines which inform the requesting peripheral that the request has been honored and the bus is relinquished by the CPU.

Features of 8257

Here is a list of some of the prominent features of 8257 −

• 1. It has four channels: channel 0, ch1, ch2, ch3 which can be used over four I/O devices.

• 2. Each channel has 16-bit address and 14-bit counter.

• 3. Each channel can transfer data up to 64kb.

• 4. Each channel can be programmed independently.

• 5. Each channel can perform read transfer, write transfer and verify transfer operations.

• 6. It operates in 2 modes, i.e., Master mode and Slave mode.

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