UNIT III: Assembly Language programming, Interrupts, Timing diagram: Questions and Notes

UNIT III: Assembly Language programming : Assembly Language programming with C/C++, Interrupt and Timing diagrams: Using Assembly Language with C/C++ for linking C/C++ into assembly language, Basic Programs – Use of BIOS and DOS Interrupts in assembly & C/C++, Interrupts of 8086 microprocessors, Timing diagram of 8086 microprocessor.

Syllabus Source:  

https://csvtu.ac.in/ew/download/b-tech-5th-semester-5/?wpdmdl=14364&refresh=63c24614a8a6f1673676308

👉Prerequisite: Study Following in detail before Attempting the Questions of this Unit.

1. INTERRUPTS?                            

2. ISR, IRET.                            

3. IVT .                         

4. TYPES OF INTERRUPTS. 

5. BLOCK DIAGRAMS OF TWO MODES of 8086 [ALSO SEE MN/MX(bar) pin diagrams].

6. Timing Diagram of Read and Write operation 8086 in Both Modes.

😃QUESTIONS : COMPILED FROM PREVIOUS YEAR CSVTU QP. :

Q. Draw Interrupt vector table of 8086 microprocessor and explain its various kinds of interrupts.

Interrupts in 8086:

While the CPU is executing a program, an interrupt breaks the normal execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).

Whenever an interrupt occurs the processor completes the execution of the current instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. 

ISR is a program that tells the processor what to do when the interrupt occurs. At the end of the ISR the last instruction should be IRET. After the execution of ISR, control returns back to the main routine where it was interrupted.   

Q. Draw and Explain the Interrupt Vector Table. 

Q. Draw and Explain the Timing Diagram of Read and Write operation of Maximum Mode of 8086 Microprocessor.

Q. Draw the Timing diagram of the read and write cycle in minimum mode.

Q. Describe function of Maximum Mode pins/signals of 8086 Microprocessor. 

Q. Describe function of Minimum Mode pins/signals of 8086 Microprocessor. 

Q. Give the Maximum Mode of Operation of 8086 Microprocessor .

Q. Give the Minimum Mode of Operation of 8086 Microprocessor.

Ans: 

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~Pradeep Kumar

 

UNIT II: Microprocessor Architecture 8086- Questions and Notes

UNIT II: Microprocessor Architecture 8086: 8086 basic block diagram, Internal Microprocessor Architecture, Real Mode Memory Addressing, Registers, pin configuration, segmentation. Data Movement Instructions: MOV, PUSH/POP, Load-Effective Address, String Data Transfers, Miscellaneous Data Transfer Instructions, Segment Override Prefix, Assembler Details. Arithmetic and Logic Instructions: Addition, Subtraction and Comparison, Multiplication and Division, BCD and ASCII Arithmetic, Basic Logic Instructions, Shift and Rotate, String Comparisons. Program Control Instructions: The Jump Group, Controlling the Flow of the Program, Procedures, and Introduction to Interrupts, Machine Control and Miscellaneous Instructions. Assembler directives, assembler instructions, Assembly Language Programming.

Syllabus Source:

https://csvtu.ac.in/ew/download/b-tech-5th-semester-5/?wpdmdl=14364&refresh=63c24614a8a6f1673676308

👉Prerequisite: Study these Topics to answer the Questions

1. 8086 Basic Block diagram.

2. 8086 Pin configuration.

3. Memory Addressing

4. 8086 Instructions: for Instructions click on this 👉Notes8086Instruction

Hint: Types of Instructions in 8086

1. Data Copy/Transfer instructions
2. Arithmetic instructions.
3. Logical instructions.
4. Shift & Rotate instructions.
5. Branch instructions.
6. Loop instructions.
7. Machine Control instructions.
8. Flag Manipulation instructions.
9. String instructions.

Questions: Compiled from Previous Year Question Paper: 

Q1. Explain BIU & EU of 8086 microprocessor.

Ans: 

BIU (Bus Interface Unit) 

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory.

It has the following functional parts − 

Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions and stores them in the instruction queue.

Fetching the next instruction while the current instruction executes is called pipelining. 

Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer register IP, which holds the address of the next instruction to executed by the EU. 

o CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored. 

o DS − It stands for Data Segment. It consists of data used by the program andis accessed in the data segment by an offset address or the content of other register that holds the offset address. 

o SS − It stands for Stack Segment. It handles memory to store data and addresses during execution. 

o ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra destination data. 

 Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be executed.

EU (Execution Unit) :

Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has no direct connection with system buses as shown in the above figure, it performs operations over data through BIU. 

Let us now discuss the functional parts of 8086 microprocessors. 

ALU:  It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations. 

Flag Register: It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags. Conditional Flags It represents the result of the last arithmetic or logical instruction executed. Following is the list of conditional flags − 

 Carry flag − This flag indicates an overflow condition for arithmetic operations. 

 Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion. 

 Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag is reset. 

 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0. 

 Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag is set to 1 else set to 0. 

 Overflow flag − This flag represents the result when the system capacity is exceeded. Control Flags Control flags controls the operations of the execution unit. Following is the list of control flags − 

 Trap flag − It is used for single step control and allows the user to execute one instruction at a time for debugging. If it is set, then the program can be run in a single step mode. 

 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition. 

 Direction flag − It is used in string operation. As the name suggests when it is set then string bytes are accessed from the higher memory address to the lower memory address and vice-a-versa. 

General purpose register:

 There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.  

 AX register − It is also known as accumulator register. It is used to store operands for arithmetic operations. 

 BX register − It is used as a base register. It is used to store the starting base address of the memory area within the data segment. 

 CX register − It is referred to as counter. It is used in loop instruction to store the loop counter. 

 DX register − This register is used to hold I/O port address for I/O instruction.  

Q2. Explain the various addressing modes of 8086 with suitable example.

Ans : click👉 Addressing modes of 8086

Types of addressing mode in 8086

1. Immediate addressing mode: MOV AX,10ABH
2. Direct addressing mode: MOV AX, [5000H]
3. Register addressing mode: MOV AX,BX
4. Register Indirect addressing mode: MOV AX,[BX]
5. Indexed addressing mode: MOV AX,[SI]
6. Register relative addressing mode: MOV AX, 50H[BX]
7. Base plus index addressing mode: MOV AX, [BX] [SI]
8. Base relative plus index addressing mode: MOV AX,50H[BX][SI]

Q3. Explain the following instructions:

(i) XCHG

(ii) CLD

(iii) AAA

(iv)CMPS

Answer: Click on this 👉📝Q3#Notes

Q4. WAP to find the smallest number among a string of 10 data bytes starting from location 2000H: 3000H and store the result in 2000H: 0500H.

For any further updates , Please visit this page on Regular Interval

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~Pradeep Kumar

UNIT I: Introduction to Basic Microprocessors Questions and Notes

UNIT I: Introduction to Basic Microprocessors: Historical Background, the Harvard and Princeton architecture, The Microprocessor-Based Personal Computer Systems. The Microprocessor 8085, 8088 basics and comparison (Block & Pin diagram only).

syllabus source:

https://csvtu.ac.in/ew/download/b-tech-5th-semester-5/?wpdmdl=14364&refresh=63c10f5a398271673596762

Prerequisite: Study the following Block diagram first to answer the Questions.

1. Block diagram for the Harvard and Princeton architecture.

2. Block Diagram for Microprocessor 8085

3. Pin Diagram for Microprocessor 8085

4. 8085 vs 8088

Questions: Compiled from previous year CSVTU QPs

1. Write the Difference between Harvard & Princeton Architecture.

👉Note: The Von Neumann (a.k.a. Princeton) architecture.

Difference Between Von Neumann and Harvard Architecture

Parameters	Von Neumann Architecture	Harvard Architecture
Definition	The Von Neumann Architecture is an ancient type of computer architecture that follows the concept of a stored-program computer.	Harvard Architecture is a modern type of computer architecture that follows the concept of the relay-based model by Harvard Mark I.
Physical Address	It uses one single physical address for accessing and storing both data and instructions.	It uses two separate physical addresses for storing and accessing both instructions and data.
Buses (Signal Paths)	One common signal path (bus) helps in the transfer of both instruction and data.	It uses separate buses for the transfer of both data and instructions.
Number of Cycles	It requires two clock cycles for executing a single instruction.	It executes any instruction using only one single cycle.
Cost	It is comparatively cheaper in cost than Harvard Architecture.	It is comparatively more expensive than the Von Neumann Architecture.
Access to CPU	The CPU is not able to read/write data and access instructions at the same time.	The CPU can easily read/write data as well as access the instructions at any given time.
Uses	This method comes to play in the case of small computers and personal computers.	This architecture is best for signal processing as well as microcontrollers.
Requirement of Hardware	As compared to Harvard Architecture, Von Neumann Architecture requires lesser architecture. It is because it only needs to reach one common memory.	This one requires more hardware. It is because it requires separate sets of data as well as address buses for individual memory.
Requirement of Space	This architecture basically requires less space.	This architecture comparatively requires more space.
Usage of Space	This architecture does not waste any space. It is because the instruction memory can utilize the left space of the data memory. It can also happen vice-versa.	This type of architecture can result in space wastage. It is because the instruction memory cannot utilize the leftover space in the data memory. It also cannot happen vice-versa.
Execution Speed	The speed of execution of the Von Neumann Architecture is comparatively slower. It is because it is not capable of fetching the instructions and data both at the same time.	The overall speed of execution of Harvard Architecture is comparatively faster. It is because the processor, in this case, is capable of fetching both instructions and data at the very same time.
Controlling	The process of controlling becomes comparatively simpler with this architecture. It is because it fetches either instructions or data at any given time.	The process of controlling becomes comparatively complex with this architecture. It is because it basically fetches both instructions and data simultaneously at the very same time.

2. Draw & Explain the Internal Architecture of 8085 in brief.

or
Explain the internal architecture of 8085 microprocessor with basic functional block.

Ans: 

3. Give Classification of Pin in 8085 with neat Diagram

Ans: Pin Diagram of 8085:

The pins of a 8085 microprocessor can be classified into seven groups:

Address bus: A15-A8

Data bus: AD7-AD0, it carries the least significant 8-bit address and data bus.

Control and status signals: Control signals are RD, WR & ALE, Status signals are IO/M, S0 & S1

Power supply: VCC & VSS.

Clock signals: 3 clock signals, i.e. X1, X2, CLK OUT

Interrupts & externally initiated signals: There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

HOLD , HLDA (HOLD Acknowledge).

Serial I/O signals: SID and SOD. 

Classification of Signals:

4. Give Comparison between Microprocessor 8085 and 8086.

Ans. Also refer the Architecture and pin diagram of 8085 and 8086.

Comparison between 8085 & 8086 Microprocessor 

  Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor. 

 Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus. 

 Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory. 

 Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue. 

 Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined architecture. 

 I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's. 

 Cost − The cost of 8085 is low whereas that of 8086 is high.

5. Give Pin Diagram of 8086 with neat label of pin Diagram.

o   8086 Microprocessor is an enhanced version of 8085 Microprocessor 

    Designed by Intel in 1976.It is a 16-bit Microprocessor, 20 address lines 16 data lines, Provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily.

6. Draw the Internal Architecture of 8086 and Explain the function of each unit of the same in brief.

Ans: 

The internal architecture of Intel 8086 is divided into 2 units: 

The Bus Interface Unit (BIU), and The Execution Unit (EU). 

8086 Architecture

Memory segmentation: 

• In order to increase execution speed and fetching speed, 8086 segments the memory. 
• Its 20-bit address bus can address 1MB of memory, it segments it into 16 64kB segments. 
• 8086 works only with four 64KB segments within the whole 1MB memory.

7. Explain the functions of the following signals of 8085.

(1)  ALE

(ii)  IO/M

(iii) RD

(iv) READY

(v) TRAP

(vi) INTR & INTA

(vii) HOLD & HLDA

(viii) RESET IN

Ans: Refer pins of 8085

Q. 8085 vs 8086 vs 8088

The architecture of 8088 is same as 8086 architecture, but there are two changes. The 8088 has a 4-byte instruction queue in place of 6-byte instruction queue in 8086 and the data bus of 8088 is 8-bit.

There is no concept of even-address bank and odd-address bank of memory in 8088.

As the data bus is 8-bit, the 8088 can access only a byte at a time. Therefore, the speed of operation of 8088 will be reduced as compared to 8086, though internal data bus of 8088 is 16 bits and it can process the 16-bit data internally. 

DIFFERENCES:

8085	8086	8088
8085 is an 8 bit microprocessor.	8086 is a 16 bit microprocessor.	8088 is a 16 bit microprocessor.
It has 8 bit data bus.	😃It has 16 bit data bus.	😃It has 8 bit data bus.
It has 8 bit ALU.	It has 16 bit ALU.	It has 16 bit ALU.
8085 does not require memory banking as it has an 8 bit data bus.	8086 requires memory banking to transfer 16 bit data at a time.	8088 does not require memory banking as it has an 8 bit data bus.
8085 performs slower memory operations as it can transfer only 8 bits in one cycle.	8086 performs faster memory operations as it can transfer 16 bits in one cycle.	8088 performs slower memory operations as it can transfer only 8 bits in one cycle.
8085 does not support pipeline architecture.	8086 supports pipeline architecture.	8088 supports pipeline architecture.
8085 has no pre-fetch queue as it does not support pipelining.	8086 has a 6 byte pre-fetch queue for pipelining.	😃8088 has a 4 byte pre-fetch queue for pipelining.
8085 has an IO/ pin to differentiate between memory and I/O operations.	8086 has an M/ pin to differentiate between memory and I/O operations.	8088 has an IO/ pin to differentiate between memory and I/O operations.
8085 has no pre-fetchqueue.	8086 BIU will fetch new bytes into the pipelining queue when 2 bytes of the queue are empty.	8088 BIU will fetch a new byte into the pipelining queue when 1 byte of the queue is empty.
8085 has 5 flags.	8086 has 9 flags.	8088 has 9 flags.

😃For further updates do visit this page regularly.

Thank you all

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~Pradeep Kumar

UNIT IV: Memory and I/O Interfacing Questions and Notes

UNIT IV: 

Memory and I/O Interfacing: Minimum and Maximum mode configuration of 8086, Memory Interface with 8086 microprocessor, Address Decoding. Basic I/O Interface: Introduction to I/O Interface, I/O Port Address Decoding. I/O Interface using peripheral devices: The Programmable Peripheral Interface 8255, Programmable Interval Timer 8254. Direct Memory Access: Basic DMA Operation and Definition.

Syllabus Source: 

https://csvtu.ac.in/ew/download/b-tech-5th-semester-5/?wpdmdl=14364&refresh=63bfa9631ce311673505123

👉Prerequisite:

We have to Learn to do following with 8086.

1. Memory Interfacing 

2. I/O Interfacing

😃Study Block Diagram of the Following (SEE CLASS NOTES TO UNDERSTAND  TOPICs) 

i. Minimum and Maximum mode configuration of 8086.

ii. Memory Interface (RAM and EPROM) with 8086.

iii. Programmable Peripheral Interface 8255.

iv. Programmable Interval Timer 8254.

v. Direct Memory Access .

Questions : Compiled from Previous CSVTU Question papers

Topic: Memory Interface (RAM and EPROM) with 8086: 

Needed: Address Mapping and Decoding Circuit

👱see class notes

Q. Design an interface between 8086 and two chips of 16K x 8 EPROM (=16KB) and two chips of 32K × 8 RAM (=32KB). Select the starting location of the EPROM suitably. RAM location must start from 00000H. 

Q. Give 8086 Memory Interfacing diagram for 32KB RAM using 16KB RAM and 16KB EPROM using 8KB EPROM, use partial Decoding. 

Q. Interface two 4K X 8 EPROMs and two 4K X 8 RAM chips with 8086 microprocessor. Select Suitable Maps. 

Q. Interface two 8K X 8 EPROMs and four 16K X 8 RAM chips with 8086 microprocessor. The address range is as follows: EPROM 1 & 2: END address is FFFFFH; RAM 1 & 2: Start Address is 10000H; RAM 3 & 4: END address is 1FFFFH. 

Q. Connect a 32kB RAM with the microprocessor 8086 using an absolute decoding with suitable address.

Example problems on memory interfacing with 8086 

(Ref: Advanced Microprocessors and Peripherals by A.K. Ray & K.M. Bhurchandi, 

McGraw-Hill, 2nd Edition.P.158- 164)

😄Beyond Syllabus:

if you want to Know how a DYNAMIC RAM  D-RAM 1-T (One Transistor ) based works , see my video:

Topic: I/O Interface with 8086: 

Needed: Block Diagrams 

Q. Explain 8254 functional Block Diagram.

Ans: 

PROGRAMMABLE INTERVAL TIMER 8254

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. 

8254 is the high speed version of the 8253. 

Application Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are: 

 Real time clock 

 Event-counter 

 Digital one-shot 

 Programmable rate generator 

 Square wave generator 

 Binary rate multiplier 

 Complex waveform generator 

 Complex motor controller

 8254 PROGRAMMABLE INTERVAL TIMER functional Block Diagram: 

It includes Three 16-bit counters COUNTER 0, COUNTER 1, COUNTER3  that can work independently in 6 different modes. 

Modes of Operation 

Mode 0: Interrupt on terminal count. 

Mode 1: Hardware Re triggerable One-Shot. 

Mode 2: Rate Generator. 

Mode 3: Square Wave Mode. 

Mode 4: Software Triggered Mode. 

Mode 5: Hardware Triggered Mode

 It is packaged in a 24-pin DIP(Dual in-line package) and requires +5V power supply. 

 It can count either in binary or BCD. 

 It’s counters can operate at a maximum frequency of 10 MHz's.

Pin functions: 

               A0, A1: The address inputs select one of the four internal registers within the 8254. 

 𝐂𝐒: Chip select enables the 8254 for programming and for reading or writing a counter. 

              Vcc: Power connects to the +5V power supply. 

              GND: Ground connects to the system ground bus. 

              GATE : The gate input controls the operation of the counter in some modes of operation. 

               D0-D7: Bidirectional three state data bus lines connected to system data bus. 

 

               CLK : The clock input is the timing source for each of the internal counters. This input is often  connected to the PCLK signal from the microprocessor system bus controller. 

               OUT: A counter output is where the waveform generated by the counter is available. 

 

 

            𝐑𝐃: Read causes data to be read from the 8254 and often connected to the 𝐼𝑂𝑅𝐶 signal. 

            𝐖𝐑: Write causes data to be written to the 8254 and often connects to the write strobe (𝐼𝑂𝑊𝐶) 

Pin.

Programming the 8254 (Control Word Format)

8254 Write operation :

The programming procedure for the 8254 is very flexible. 

Only two conversion need to be remember. 

1) For each Counter, the Control Word must be written before the initial count is written. 

2) The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). 

With a clock and an appropriate gate signal to one of the counters, the above steps should start the counter and provide appropriate output according to the control word.

Q. Explain the functional block diagram of 8255 PPI.

Ans:

8255 PPI

8255 PPI (Programmable Peripheral Interface)

It is a programmable peripheral interface, which means it is a programmable device used to interface I/O devices with the processor.

8255 is a programmable I/O device that acts as interface between peripheral devices and the microprocessor for parallel data transfer. 

8255 PPI (programmable peripheral interface) is programmed in a way so as to have transfer of data in different conditions according to the need of the system.

The common applications of 8255 are: 
 

• Traffic light control
• Generating square wave
• Interfacing with DC motors and stepper motors

Architecture of 8255: 

In 8255, 

The three ports are Port A, Port B and Port C and as each port has 8 lines, but the 8 bits of port C is divided into 2 groups of 4-bit each. These are given as port C lower i.e., PC3 – PC0 and port C upper i.e., PC7 – PC4. 

And are arranged in group of 12 pins each thus designated as Group A and Group B.

  

Modes of 8255 – It works in two modes: 
 

1. Bit set reset (BSR) mode.
2. Input/output (I/O) mode.

I/O mode is further classified into:

Mode 0: Simple input/output
Mode 1: Input output with handshaking

Mode 2: Bidirectional I/O hand shaking

To know in which mode the interface is working we need to know the value of Control word. Control word is a part of control register in 8255 which specify an I/O function for each port. This is format of control word 8255.

Example: 

Q. Explain the Basic DMA operation.

Ans: 

Microprocessor - 8257 DMA Controller

Definition: DMA or Direct Memory Access Controller is an external device that controls the transfer of data between I/O device and memory without the involvement of the processor. It holds the ability to directly access the main memory for read or write operation.

DMA controller was designed by Intel, to have the fastest data transfer rate with less processor utilization.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

• 1. Initially, when any device has to send data between the device and the memory, the device has to send DMA request (DRQ) to DMA controller.

• 2. The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.

• 3. Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control over bus and acknowledges the HOLD request through HLDA signal.

• 4.Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses between the CPU, memory, and I/O devices.

  

• 8257:
• DRQo- DRQ3: These are the four individual channel DMA request inputs, used by the peripheral devices for requesting the DMA services. The DRQo has the highest priority while DRQ3 has the lowest one, if the fixed priority mode is selected. 
• DACKo- DACK3: These are the active- low DMA acknowledge output lines which inform the requesting peripheral that the request has been honored and the bus is relinquished by the CPU.

Features of 8257

Here is a list of some of the prominent features of 8257 −

• 1. It has four channels: channel 0, ch1, ch2, ch3 which can be used over four I/O devices.

• 2. Each channel has 16-bit address and 14-bit counter.

• 3. Each channel can transfer data up to 64kb.

• 4. Each channel can be programmed independently.

• 5. Each channel can perform read transfer, write transfer and verify transfer operations.

• 6. It operates in 2 modes, i.e., Master mode and Slave mode.

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Thank you all

keep Visiting this page for further updates.

Yours's

Pradeep Kumar

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