CSA UNIT 2 ARITHEMATIC

CSA UNIT 2 # ARITHEMATIC

Questions and Answers (as per previous year CSVTU QP): 

1. Explain the working of 4 bit Fast Adder Carry Look Ahead Adder with neat Diagram.

Ans:  see class notes : Click 👉 Lookahead carry adder

OR

What is a Carry Look-ahead Adder?

A digital computer must contain circuits which can perform arithmetic operations such as addition, subtraction, multiplication, and division. Among these, addition and subtraction are the basic operations whereas multiplication and division are the repeated addition and subtraction respectively.

To perform these operations ‘Adder circuits’ are implemented using basic logic gates. Adder circuits are evolved as Half-adder, Full-adder, Ripple-carry Adder, and Carry Look-ahead Adder.

2. Give the Flow table for the register’s Content used in implementing above Algorithm.

Ans : For Algorithm and Flowchart , Click 👉 Booth's Algorithm

OR

The booth algorithm is a multiplication algorithm that allows us to multiply the two signed binary integers in 2's complement, respectively. It is also used to speed up the performance of the multiplication process. It is very efficient too.

Working on the Booth Algorithm

1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.
2. Initially, we set the AC and Q_{n + 1} registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is continuously decremented till equal to the number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Q_n+1 shows the incremented bit of Qn by 1.
5. On each cycle of the booth algorithm, Q_n and Q_{n + 1} bits will be checked on the following parameters as follows:
   1. When two bits Q_n and Q_{n + 1} are 00 or 11, we simply perform the arithmetic shift right operation (ashr) to the partial product AC. And the bits of Qn and Q_{n + 1} is incremented by 1 bit.
   2. If the bits of Q_n and Q_{n + 1} is shows to 01, the multiplicand bits (M) will be added to the AC (Accumulator register). After that, we perform the right shift operation to the AC and QR bits by 1.
   3. If the bits of Q_n and Q_{n + 1} is shows to 10, the multiplicand bits (M) will be subtracted from the AC (Accumulator register). After that, we perform the right shift operation to the AC and QR bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.

3. Multiply (+5) and (-7) using Booth’s Algorithm. 

Ans: Click 👉 5 * -7

4. Multiply (+5) and (+7) using Booth’s Algorithm.

Ans: Click 👉 +5 * +7

5. Explain the circuit for Binary Parellel Adder/Subtractor circuit using full Adder.

Ans: Click 👉Adder cum Subtractor circuit