QUICK REFERENCE HANDOUT FOR EXAMS
Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)
VHDL Basics Handouts:
UNIVERSITY: Chhattisgarh Swami Vivekananda Technical University, Bhilai (C.G.)
SUBJECT: Digital Electronics
SEM: THIRD
CODE: B022314(022)
Syllabus Link:
click here 👉https://csvtu.ac.in/ew/download/b-tech-3rd-semester-3/?wpdmdl=12485&refresh=6401acff29d151677831423
Prerequisite:
1. See Mealy & Moore Machine in FSM.
2. LEARN VHDL SYNTAX AND OPERATORS
2. Study the Body of VHDL program.
3. LEARN DIFFERENT STYLES OF MODELLING: DATAFLOW, BEHAVIOURAL,STRUCTURAL STYLES.
IMPORTANT KEY POINTS:What is VHDL?
VHSIC Hardware Description Language
Very High Speed Integrated Circuit
• IEEE standard
– IEEE 1076-1987
– IEEE 1076-1993
History of VHDL
• Designed by IBM, Texas Instruments, and
Intermetrics as part of the DoD funded VHSIC program
•
Standardized by the IEEE in 1987: IEEE 1076-1987
•
Enhanced version of the language defined in 1993:
IEEE 1076-1993
•
Additional standardized packages provide
definitions of data types and expressions of timing data
–
IEEE 1164 (data types)
–
IEEE 1076.3 (numeric)
–
IEEE 1076.4 (timing)
•
Hardware description languages describe a
system
–
Systems can be described from many different
points of view
•
Behavior: what does it do?
•
Structure: what is it composed of?
•
Functional properties: how do I interface to it?
• Physical properties: how fast is it?
VHDL Syntax:
Questions: Compiled from CSVTU previous year Question Papers
1. Discuss the various operators used in VHDL.
ANS:
2. Write short notes on Mealy and Moore machine.
or
Explain Mealy machine with example.
ANS:
While diving into the basic difference between the two, let's first understand finite state machines since Mealy and Moore both are the techniques used in finite state machines. The input combinational circuit in synchronous sequential circuits is made up of a series of logic gates, with flip flops serving as memory elements.
The synchronous sequence machine is described by the finite state machine (FSM), which is an abstract model. In a sequential circuit, the output is determined by the current input as well as previous history, necessitating an endless storage capacity.
Finite state machines are utilized because machines with infinite storage capacity are impossible to implement. Finite state machines are sequential circuits with a finite number of ways in which their past history might affect their future behavior.
Machines with a finite number of states are known as finite state machines. There are a limited number of memory devices in any finite-state system. We can construct a periodic sequence of fewer than or equal to n-states using an n-state machine.
There are two types of finite state machines (FSM). The way the output is generated is the main difference between them.
- Moore Machine
- Mealy Machine
The fundamental difference between the Mealy and Moore machines is that the dependency of output is on the current state and input. The current output of the Moore machine is solely determined by its current state. The current output of the Mealy machine is determined by the present state and present external inputs. Moore and Mealy machines are quite complex machines.
Moore and mealy machines are generators. Moore and Mealy machines have no knowledge of a final state because they aren't used to recognize languages. Moore and Mealy machines are finite-state deterministic devices.
3. Write a program in VHDL using Data flow modelling for half adder.
Logical Expressions:
Sum <= A XOR B
Carry Out <= A AND B
VHDL PROGRAM/CODE:
The VHDL code for Half Adder is given below where the
😎Data Flow Modelling is used as it involves only simpler equations.
library IEEE; use IEEE.std_logic_1164.all;
entity half_adder is port(A,B: in std_logic; sum,carryout: out std_logic ); end half_adder;
architecture flow of half_adder is
begin
sum<= A xor B;
carryout<=A and B;
end flow;The libraries are declared, 4. Write a program in VHDL using Behavioral modelling for AND gate.
ANS:
Logic Development for AND Gate: The AND logic gate can be realized as follows –
The truth table for AND Gate is:
| A | B | Y = A AND B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
VHDL PROGRAM:
😎NOTE: Behavioral modelling USES TRUTH TABLE
use IEEE.std_logic_1164.all;entity AND_1_BEV is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end AND_1_BEV;
architecture Behavioral of AND_1_BEV is
begin process (A, B)
begin
if(A='1' and B='1') then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;
5. Write difference between Moore and Mealy Machine.
ANS:
Types of finite state machines
- Melay Machine
- Moore Machine
Difference between melay vs moore machine
Moore Machine
- More number of states in moore compared to melay for same fsm.
- States changes after 1 clock cycle. Latency = 1.
- Synchronous output. Because the states are determined in a process.
- States are output.
Mealy Machine
- Less number of states in mealy compared to moore for same fsm.
- State transition on the same clock cycle. Latency = 0.
- Asynchronous output.
- Transition are output.
6. Explain lexical element and data object types in VHDL.
7. Write syntax for:
(i) entity and
(ii) architecture in VHDL.
ANS: SEE BLOCK DIAGRAMS ABOVE WITH ANY ONE EXAMPLE OF DIGITAL CIRCUIT.
Refer Book:
1. VHDL: PROGRAMMING BY EXAMPLE - by Douglas L. Perry
2. Digital Design | With an Introduction to the Verilog HDL, VHDL, and System Verilog - by M. Morris Mano
3. A Vhdl Primer - by Bhasker
4. Fundamentals of Digital Logic with VHDL Design - by Stephen Brown and Zvonko Vranesic
5. Circuit Design and Simulation With VHDL - by Pedroni V.A
